1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a non-volatile memory device such as a local silicon-oxide-nitride-oxide-silicon (SONOS) type semiconductor memory device.
2. Description of the Related Art
In recent years, non-volatile memory device such as SONOS devices have been developed. Unlike a gate stack type nonvolatile memory device that employs a floating gate, the SONOS device employs a charge trapping layer formed of silicon nitride instead of a floating gate in forming a memory cell.
Local SONOS devices are formed by defining a localized region of the charge trapping layer under a gate in which the gate and the charge trapping layer are partially overlapping only on a defined length.
A localized charge trapping layer was disclosed in U.S. Pat. No. 5,408,115 to Kno-Tung Chang, “Self Aligned, Split Gate EEPROM Device” registered on Apr. 18, 1995. In this method a control gate and a charge trapping layer are formed by a self alignment process.
FIG. 1A is a cross-sectional view of a cell configuration of a conventional local SONOS device.
FIG. 1B is a cross-sectional view showing problems with the conventional local SONOS device.
Referring to FIG. 1A, a conventional local SONOS device can comprise an ONO layer 20, i.e., a first silicon oxide layer 21, a locally defined silicon nitride layer 23, a second silicon oxide layer 25 on a silicon semiconductor substrate 10, and a gate 30 on top of the ONO layer 20.
However, when forming the conventional local SONOS device, lengths 41 and 42 along which the gate 30 is above the silicon nitride layer 23 and lengths 43 and 44 along which the silicon nitride layer 23 is not beneath the gate 30 in each cell may be different as result of a misalignment during a photo lithography process.
Referring to FIG. 1B, the lengths 41′ and 42′ on which the gates are above the silicon nitride layer 23 may not be the same if a photo misalignment occurs during a first photo lithography process for defining the local silicon nitride layer 23 and a second photo lithography process for patterning the gate 30.
Accordingly, the lengths 43′ and 44′ on which the silicon nitride layer 23 is not beneath the gates may also be different.
Such a photo misalignment can cause a difference in an effective length of the control gate 30 between the cells and a difference in an effective length of the local silicon nitride layer 23 for charge trapping. These differences between cell 1 and cell 2 results in an undesirable nonuniformity of operating characteristics between the cells.